Cache-Controlled Physical Memory--xkphys

Cache-Controlled Physical Memory--xkphys

One-quarter of the 64-bit address space--all addresses with bits 63:62 containing 10--are devoted to special access to the 1 TB physical address space. In 64-bit mode this space replaces the kseg0 and kseg1 spaces used in 32-bit mode. Addresses in this space are interpreted as shown in Figure 1-9.

Figure 1-9 : Address Decoding for Physical Memory Access Bits 39:0 select a physical address in a 1 TB range. As a result, a system operating in 64-bit mode can access a much larger physical address space than the 512 MB space allowed by kseg0. This permits more physical memory to be installed, and it gives more freedom in assigning device and bus addresses.

Bits 57:40 must always contain 0. Bits 61:59 select the hardware cache algorithm to be used. The only values defined for these bits are summarized in Table 1-3.

Cache Algorithm Selection
Address 61:59 Algorithm Meaning
010 Uncached This is the 64-bit equivalent of kseg1 in 32-bit mode--uncached access to physical memory.
110 Cacheable coherent exclusive on write This is the 64-bit equivalent of kseg0 in 32-bit mode--cached access to physical memory, coherent access in a multiprocessor.
011 Cacheable non-coherent Data is cached; on a cache miss the processor issues a non-coherent read (one without regard to other CPUs).
100 Cacheable coherent exclusive Data is cached; on a read miss the processor issues a coherent read exclusive.
101 Cacheable coherent update on write Same as 110, but updates memory on a store hit in cache.
111 Uncached Accelerated Same as 010, but the cache hardware is permitted to defer writes to memory until it has collected a larger block, improving write utilization.

Cache Algorithm Selection
Address 61:59	Algorithm	Meaning
010	Uncached	This is the 64-bit equivalent of kseg1 in 32-bit mode--uncached access to physical memory.
110	Cacheable coherent exclusive on write	This is the 64-bit equivalent of kseg0 in 32-bit mode--cached access to physical memory, coherent access in a multiprocessor.
011	Cacheable non-coherent	Data is cached; on a cache miss the processor issues a non-coherent read (one without regard to other CPUs).
100	Cacheable coherent exclusive	Data is cached; on a read miss the processor issues a coherent read exclusive.
101	Cacheable coherent update on write	Same as 110, but updates memory on a store hit in cache.
111	Uncached Accelerated	Same as 010, but the cache hardware is permitted to defer writes to memory until it has collected a larger block, improving write utilization.

Only the 010 (uncached) and 110 (cached) algorithms are implemented on all systems. The others may or may not be implemented on particular systems.

Bits 58:59 must be 00 unless the cache algorithm is 010 (uncached) or 111(uncached accelerated). Then bits 58:59 can in principle be used to select four other properties to qualify the operation. No present Silicon Graphics computer system supports these properties, so bits 58:59 always contain 00 at this time.

Portions of xkphys and xkseg can be mapped to user process space by the mmap() function. This is covered in more detail under "Memory Use in User-Level Drivers".